1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory and more particularly to a flash memory. Further, this invention relates to a manufacturing method of the nonvolatile semiconductor memory.
2. Description of the Related Art
Nonvolatile semiconductor memories, for example, flash memories are mounted as storage devices on various electronic devices.
The flash memory has a memory cell array area for data storage and a peripheral circuit area in which a control circuit for the memory cell array area is arranged as main construction areas. Further, memory cells and select gate transistors are arranged in the memory cell array area and peripheral transistors such as high-breakdown-voltage (high-voltage) metal-insulator-semiconductor (MIS) transistors and low-breakdown-voltage (low-voltage) MIS transistors are arranged in the peripheral circuit area.
Up to now, the memory cell having the structure in which a floating gate electrode is used as a charge storage layer is dominantly used. Recently, for example, memory cells with a metal-oxide-nitride-oxide-semiconductor (MONOS) structure using an insulating layer as a charge storage layer are positively developed in order to increase the storage capacity and attain miniaturization of memory cells caused by the increase in the storage capacity (for example, see Jpn. Pat. Appln. KOKAI Publication No. 2002-324860).
In a general flash memory manufacturing method, memory cells, select gate transistors and peripheral transistors are substantially simultaneously formed to reduce the number of manufacturing steps. If flash memories having MONOS memory cells are formed by use of the above manufacturing method, select gate transistors and peripheral transistors are formed with the gate structures having insulating layers that are the same as the charge storage layers on the gate insulating films thereof. With this structure, if voltage is applied to the gate electrode, charges are stored on the insulating layer (charge storage layer), the threshold voltages of the select gate transistors and peripheral transistors are varied and a problem occurs in the operations of the transistors and a circuit configured by the transistors.
Therefore, if memory cells and MIS transistors are formed by using different manufacturing steps in order to form the select gate transistors and peripheral transistors with the MIS structure having no charge storage layer, the number of manufacturing steps will be increased. Further, a new area must be provided near the boundary between the forming areas in order to securely attain a process margin of each forming area. In addition, since the memory cell has a charge storage layer and block insulating film and the select gate transistors and peripheral transistors have neither the charge storage layer nor the block insulating film, a difference in level occurs between the upper end of the gate electrode of the memory cell and the upper end of the gate electrode of the select gate transistor or peripheral transistor. Due to the difference in level, the degree of processing difficulty in the manufacturing process becomes extremely high.